Galvanically isolated dc-dc circuit converter with data communication, corresponding system and corresponding method

ABSTRACT

A DC-DC converter includes a power oscillator connected to a first transformer winding, and a channel conveying a data stream through galvanic isolation by power signal modulation. A rectifier rectifies the power signal to produce a DC voltage. A comparator produces an error signal from the DC voltage and a reference voltage. An analog-to-digital converter converts the error signal to a digital power control value. A multiplexer multiplexes the digital power control value with the data stream to obtain a multiplexed bitstream. A transmitter driven by the multiplexed bitstream performs amplitude modulation of the power signal at a second transformer winding. A receiver connected to the first winding demodulates the amplitude modulated power signal. A demultiplexer demultiplexes the data stream and the digital power control value. A digital-to-analog converter converts the digital power control value to an analog control signal for the power oscillator.

PRIORITY CLAIM

This application claims the priority benefit of Italian Application forPatent No. 102018000000830, filed on Jan. 12, 2018, the content of whichis hereby incorporated by reference in its entirety to the maximumextent allowable by law.

TECHNICAL FIELD

The description relates to galvanically isolated DC-DC convertercircuits.

One or more embodiments may apply to an embodiment with an isolationtransformer manufactured on a stand-alone chip using a dedicatedprocess.

One or more embodiments may apply to an embodiment with an isolationtransformer manufactured on a chip of including an oscillator of theconverter with an integrated approach.

BACKGROUND

A large number of applications require transferring power and datathrough a galvanic isolation barrier of several kilovolts.

Applications of such systems are in several fields such as industrial(e.g., high-side gate drivers), medical (e.g., implantable devices),isolated sensor interfaces, and lighting. The industry standard VDE0884-10 has been developed to expressly take into account theavailability of highly integrated semiconductor isolators withmicro-scale isolation barriers, either using magnetic or capacitivetransfer techniques. Either post-processed or integrated isolationcapacitors can be adopted to perform galvanically isolated datacommunication.

Commercial isolated DC-DC converters typically adopt post-processedisolation transformers by using an architecture which includes: anisolated link for the power transmission (isolated power channel), whichtypically includes a VHF power oscillator, an isolation transformer, anda power rectifier; a further isolated link for the feedback path used tocontrol the output power (typically by a PWM modulation of the poweroscillator); and a plurality of dedicated isolated links, each onerespectively for one of the data channels.

These architectures require at least three isolation transformers, onefor the power channel, one for the feedback control channel, and one forthe data channel.

There is a need in the art to address the drawbacks of priorimplementations, by facilitating regulation of the power whilemaintaining a single channel through the galvanic isolation barrier.

SUMMARY

In one or more embodiments, a stream of data conveyed through anisolation galvanic barrier of a converter circuit by modulating thepower signal includes n-data channel bits and a digital word includingpower control bits.

In one or more embodiments, the converter circuit includes: a rectifierconnected to the second winding of the transformer configure to obtainan output DC voltage by rectifying of the received power AC signal onthe second winding; a comparator receiving as input the output DCvoltage and a reference voltage value producing an error signal; ananalog to digital converter configured to convert the error signal in adigital word; a multiplexer multiplexing the digital word with n-channeldata to produce a multiplexed bitstream; a transmitter configured toperform the amplitude modulation of the power signal driven by themultiplexed bitstream; a demodulator connected to the first winding andconfigured to demodulate the amplitude modulated signal at such firstwinding; a demultiplexer configured to demultiplex the n-data channelsand power control bit data (digital word); and a digital to analogconverter configured to convert the power control bits to an analogcontrol signal, the analog control signal being a control voltage of thepower oscillator for power regulation.

In comparison with certain known arrangements, one or more embodimentsmay facilitate achieving regulation of the power while maintaining asingle channel through the galvanic isolation barrier.

One or more embodiments may offer one or more of the followingadvantages: increasing the level of integration, reducing the siliconarea and system cost thanks to the capability to transfer power, controlsignal, and data using only one isolation barrier implemented by aproper transformer; compatibility with the implementation of a commonmode transient injection (CMTI) rejection block (moreover, the use of acurrent-controlled power oscillator in the proposed implementationfurther improves the CMTI rejection performance); and avoiding, by usinga single carrier on a single isolated link, the cross-talk phenomenabetween power and data channels (this makes it possible to transferhigher power than the traditional solutions based on two separatedlinks).

One or more embodiments may thus provide a galvanically isolated DC-DCconverter circuit including a galvanic isolation barrier across which apower signal is transmitted, the DC-DC converter circuit comprising apower oscillator connected to a first winding of an isolationtransformer, and at least a data communication channel on which a streamof data is conveyed through the galvanic isolation barrier (GI) bymodulating the power signal. A transmitter performs an amplitudemodulation of the power signal at a secondary winding of thetransformer, and a rectifier connected to the second winding of thetransformer is configured to obtain an output DC voltage by rectifyingof the received power AC signal on the second winding. A comparatorreceives as input the output DC voltage and a reference voltage valueproducing a voltage error signal, and an analog to digital converter isconfigured to convert the error signal in a digital power control value.A multiplexer multiplexes together the digital power control value withthe n-channel data to obtain a multiplexed bitstream. A transmitter isconfigured to perform the amplitude modulation of the power signaldriven by the multiplexed bitstream, and a receiver is connected to thefirst winding and configured to demodulate the amplitude modulatedsignal at such first winding. A demultiplexer is configured todemultiplex the n-data channels and digital power control value, and adigital to analog converter is configured to convert the digital powercontrol value in an analog control signal supplied as control voltage ofthe power oscillator for power regulation.

In one or more embodiments, the isolation transformer is on a dedicatedstand-alone chip.

In one or more embodiments, the isolation transformer is on the samechip of the power oscillator.

In one or more embodiments, the converter includes, between the firstwinding and the receiver, a CMT rejection block of the isolationtransformer configured to reduce the effects of CMT in the amplitudemodulated signal.

In one or more embodiments, the isolation transformer uses central tapsconnected to power supply and ground on the power oscillator chip andrectifier chip, respectively, to guarantee a low impedance path for thecurrent injected by CMT events.

In one or more embodiments, the analog to digital converter comprises aPWM generator, whose PWM output signal is sampled and multiplexedtogether with the n channel data.

In one or more embodiments, the digital to analog converter comprises afilter configured to extract a DC component from the PWM signal, whichregulates the transmitted power by the control voltage terminal.

In one or more embodiments, the power oscillator is configured as poweroscillator with resonant load.

In one or more embodiments, the power oscillator is associated with acircuit, for regulating the bias of the power oscillator, including abias MOSFET configured to provide a minimum bias current for theoperation of the oscillator under the control of a bias voltage and aregulation MOSFET configured to adjusting the bias current under thecontrol of the regulation voltage.

In one or more embodiments, the power oscillator includes a switcharrangement to feed a given digital value to the multiplexer under thecontrol of a timing signal based on a reference clock signal. The poweroscillator also includes a corresponding switch arrangement to feed thedigital value to a circuit arrangement performing a reset of thedemultiplexing operation on the basis of the occurrence of the givendigital value in the received bitstream, the timing signal identifying aclock training phase to synchronize the multiplexer and demultiplexer.

In one or more embodiments a method of performing an isolated DC-DCconversion may include transmitting across a galvanic isolation barriera power signal of a converter comprising a power oscillator connected toa first winding of an isolation transformer, and implementing at least adata communication channel by conveying a stream of data through thegalvanic isolation barrier by modulating the power signal. Themodulating may include performing an amplitude modulation of the powersignal at a secondary winding of the transformer. This provides forobtainment of an output DC voltage by rectifying the received power ACsignal at secondary winding of the transformer receiver side of theconverter, comparison of the output DC voltage with a reference voltagevalue to produce an error signal, conversion of the error signal in adigital power control value, multiplexing together of the digital powercontrol value with the n-channel data obtaining a multiplexed bitstream,driving with the multiplexed bitstream the transmitter performing theamplitude modulation of the power signal, demodulation of the amplitudemodulated signal received at the first winding, demultiplexing of then-data channels and power control bit value, and conversion of thedigital power control value in an analog control signal supplied ascontrol voltage (V_(CTRL)) of the power oscillator for power regulation.

In one or more embodiments, the method may include performing asynchronization of the multiplexing operation and demultiplexingoperation by feeding a given digital value to the multiplexing operationunder the control of a timing signal identifying a clock training phasebased on a reference clock signal and correspondingly feeding the givendigital value to perform a reset of the demultiplexer. In particular,the counter drives the demultiplexer on the basis of the occurrence ofthe given digital value in the received bitstream.

BRIEF DESCRIPTION OF THE DRAWINGS

One or more embodiments will now be described, by way of example only,with reference to the annexed figures, wherein:

FIG. 1 is an exemplary representation of a possible context of use ofembodiments of DC-DC converter circuits disclosed herein;

FIG. 2 is a block diagram of an embodiment of a DC-DC converter;

FIG. 3 is a block diagram of an embodiment of a DC-DC converter;

FIG. 4 is a block diagram of an embodiment of a DC-DC converter;

FIG. 5 is a block diagram of an embodiment of a DC-DC converter inoperation; and

FIG. 6 is a block diagram of an embodiment of a common mode transientrejection circuit such as may be used in embodiments of DC-DC convertersherein.

DETAILED DESCRIPTION

In the ensuing description, one or more specific details areillustrated, aimed at providing an in-depth understanding of examples ofembodiments of the instant description. The embodiments may be obtainedby one or more of the specific details or with other methods,components, materials, and so on. In other cases, known structures,materials or operations are not illustrated or described in detail sothat certain aspects of embodiment will not be obscured.

Reference to “an embodiment” or “one embodiment” in the framework of thepresent description is intended to indicate a particular configuration,structure, characteristic described in relation to the embodiment iscompliance in at least one embodiment. Hence, phrases such as “in anembodiment” or “in one (or more) embodiments” that may be present in oneor more points in the present description do not necessarily refer toone and the same embodiment. Moreover, particular conformation,structures or characteristics as exemplified in connection with any ofthe figures may be combined in any other way in one or more embodimentsas possibly exemplified in other figures.

The references used herein are provided merely for convenience and hencedo not define the extent of protection or the scope of the embodiments.

Throughout this description reference will be made to various documents.Captions to these documents will include a number between squareparentheses (e.g. [X]), where the number between square parentheses isthe number which identifies the captioned document in the LIST OFREFERENCES CITED IN THE DESCRIPTION reproduced at the end of thisdescription.

One or more embodiments may provide a DC-DC converter circuit 110 with a(galvanic) isolation barrier GI in a system having the general layoutexemplified in FIG. 1, namely a system including a first unit 10 and asecond unit 12 having respective supply lines V_(DD1), V_(DD2) andgrounds GND₁ and GND₂. A common mode signal V_(CM) may be establishedbetween the two grounds GND₁ and GND₂ which may be exposed to groundshifts and thus to transients or CMTs (e.g. dV_(CM)/dt).

One or more embodiments may apply to systems where power transfer PT isprovided from the unit 10 through a converter circuit to the unit 12while bidirectional data transfer DT may occur between the unit 10 andthe unit 12.

Human/data interfaces, bus/network controllers, includingmicrocontroller units (μCUs) may be exemplary of units 10.

Sensor interfaces, gate drivers, medical equipment, and communicationnetwork devices may be exemplary of units 12.

Either post-processed or integrated isolation capacitors can be used inproviding galvanically isolated data communication [1]. Capacitiveisolators may use a two-chip approach (i.e., RX and TX), exploitingeither RF amplitude modulation or pulsed transmission. However,capacitive isolator techniques may not be able to provide power transferdue to the detrimental voltage partition at the input of power rectifierand consequent degradation of power efficiency, especially when highgalvanic isolation is desired.

Transformer-based isolators can also be used for data transmission.Isolation transformers may be implemented by post-processing steps [2].

Post-processed isolation transformers may also be exploited forhigh-efficiency power transfer [3]-[5] by using a dedicated link formedby a power oscillator (i.e., the DC-AC converter) and a rectifier (i.e.,the AC-DC converter).

Certain integrated transformers capable of sustaining several kilovoltshave been also developed [6]. Based on this technology, galvanicallyisolated data transfer systems were made available [7], whilehigh-efficiency power transfer has been recently demonstrated [8]-[11].

The main advantages and drawbacks of various different isolationapproaches are summarized in the table below.

Isolation approaches Main features Drawbacks Integrated On-chip galvanicisolation Trade-off in terms of capacitors Data transfer availablecost/area and isolation CMT additional circuitry to be usedPost-processed Data and power transfer available Low level ofintegration transformer High CMT immunity for data transfer Efficiencydegradation at High galvanic isolation rating high isolation ratingIntegrated On-chip galvanic isolation Limited isolation ratingtransformers Data transfer products due to oxide thickness High CMTimmunity for data transfer Power transfer demonstrated

Commercial isolated DC-DC converters typically adopt post-processedisolation transformers by using an architecture which includes: anisolated link for the power transmission (isolated power channel), whichis typically formed from a VHF power oscillator, an isolationtransformer and a power rectifier; a further isolated link for thefeedback path used to control the output power (typically by a PWMmodulation of the power oscillator); and a plurality of dedicatedisolated links, one for each data channel.

These architectures use at least three isolation transformers, one forthe power channel, one for the feedback control channel and one for thedata channel.

An alternative architecture for an isolated DC-DC converter is shown inU.S. Pat. No. 9,306,614 [12]. The main idea is to also use the isolatedpower channel for a bidirectional (half-duplex) data communication by anASK modulation of the power signal at the primary or the secondarywindings of the isolation transformer. Proper demodulation circuitriesare included to recover data and clock bit stream on both the first andsecond interfaces.

In this application, however, a variable power functionality is notcompatible with data transmission implemented by ASK modulation on thepower channel. Also, data communication utilizes the presence of thepower signal and this is not compatible with typical power control thatexploits an on/off modulation (i.e., PWM modulation, Bang-Bang controlscheme) of the power oscillator to preserve efficiency. Thus, such animplementation cannot be used when a variable/controlled output power isdesired. Therefore, an output voltage regulator would be used.

Also, inherent CMT rejection performance is poor. To transfer power withgood efficiency involves large isolation power transformers and hencehigh parasitic capacitances between primary and secondary windings ofthe isolation transformer. This is against the desire for a high CMTrejection because the injected currents due to CMTs are proportional toparasitic primary-to-secondary capacitances (i.e. I=C dV/dt).

However, in several applications, along with power and datatransmission, the regulation of the transmitted power is to be used. Apossible implementation uses two separated isolated channels as shown inthe publication of Z. Tan et al., “A fully isolated delta-sigma ADC forshunt based current sensing,” IEEE Journal of Solid-State Circuits, vol.51, October 2016 [13]. In the architecture there discussed, a firstisolated channel is used for a power transmission and a second channelfor data and power control feedback transmission. Moreover,micro-transformers are used to implement the two galvanically isolatedlinks.

However, this implementation brings with it a high occupation area withhigher cost because at least two separated isolated links are used totransfer regulated power and data. Two isolation transformers are usedto help guarantee an isolated and regulated DC-DC conversion togetherwith a high speed data transmission. These architectures use a multichipimplementation (also 5-6 chips) in which the two isolation componentsgenerally occupy a large area. There is an increase in the complexity ofthe system in package and therefore at a higher cost. Furthermore, thepresence of two isolated channels can produce a cross-talk phenomenathat hinders data communication.

Given the state-of-the-art of isolated DC-DC converters with datacommunication, it is clear that reducing the number of isolated linkswould represent an important advance in terms of size and costs. Ofcourse, this has to be implemented without significantly affecting theoverall performance of the converter. The architecture disclosed hereinuses only one isolated link to transfer power and n-channels datamultiplexed with the power control signal, thus overcoming the drawbacksof conventional designs.

For the sake of simplicity and ease of understanding, the precedingdescription was provided with reference to embodiments wherein the firstunit 10 and the second unit 12 include a transmitter 118 and a receiver120, with data transmission DT assumed to take place (uni-directionally)from the transmitter 118 to the receiver 120. The transmitter 118 andreceiver 120 are included in a galvanically isolated DC-DC converter 110with data transmission using an isolated link to transfer power withhigh efficiency and a feedback link to control the output DC voltage andfurther support a data communication channel.

Thus, one or more embodiments may provide: a second unit 12 comprising atransmitter 118, as shown in FIG. 2 described in the following, fortransmitting signals over a carrier DT; a first unit 10 comprising areceiver 120 for receiving the signals over a carrier DT transmitted bythe transmitter 118; and a converter circuit 110 set between thetransmitter 118 and the receiver 120, in particular comprising thetransmitter 118 and the receiver 120, providing a galvanically isolatedtransmission channel for the signals over a carrier DT between thetransmitter 118 and the receiver 120.

FIG. 2 is a block diagram showing a general implementation of thegalvanically isolated DC-DC converter circuit 110 with data transmissionusing an isolated link to transfer power and a feedback link to controlthe output DC voltage and further support a data communication channel.

With the numerical reference 112 is indicated a power oscillatorincluded in the converter circuit 110, which outputs an alternatingcurrent voltage V_(I), the amplitude of which is regulated by a controlvoltage V_(CTRL). The alternating current voltage V_(i), is supplied toa first, primary, winding 111 p of an isolation transformer 111 whichrepresents a galvanic isolation barrier. A secondary winding 111 s isconnected to a rectifier 113, the output of which, through an outputfilter R_(L), C_(L), forms a DC output voltage V_(o). Thus, the galvanicisolation barrier is implemented by an isolation transformer 111 usedfor the power transfer, according to the scheme based on a poweroscillator 112 and a rectifier 113.

The output voltage V_(o) is picked up by a partition circuit 114 whichfeeds a comparator 115, which receives at its other input a referencevoltage REF. In this way, the output DC voltage V_(o), obtained byrectification at rectifier 113 of the received power AC signal, iscompared with the reference voltage, REF, and produces an error signal,ε.

The error signal E is then converted into a digital word, whichrepresents a digital power control value P, by an analog to digitalconverter 116 and fed to an input of a multiplexer 117, which receivesat its other inputs n data streams D1, D2, Dn, forming the n-channeldata. The multiplexer produces at its output a bitstream TBT, in whichthe power control value P and the data streams D1, D2 . . . Dn aremultiplexed. The bit stream TBT output by the multiplexer 117 is used todrive a modulation transmitter 118 which is configured to apply anamplitude modulation to the AC power signal, specifically an ASK(Amplitude Shift Keying) modulation, at the second winding 111 s of theisolation transformer 111 by a load mismatch. Thus, data transmission isimplemented by a transmitter circuit performing an amplitude modulationof the power signal at the secondary winding by means of a load mismatch

In particular, the transmitter 118, as better detailed with reference toFIG. 5, includes a modulator 118 b, implemented by NMOS switches, whichshunt to ground two detuning capacitors, connected to the two ends ofthe secondary winding 111 s, under the control of a signal supplied byan encoder 118 a. These capacitors are used to detune the secondarywinding 111 s of the isolation transformer 111, i.e. they change thereactive part of the impedance (as happens with the backscattering in aRFID), thus producing an amplitude modulation at the primary winding 111p, indicated as OUT. Such amplitude modulation OUT is received at thefirst winding through a CMT (Common Mode Transient) rejection circuit(CMTR) 119, which reduces the effects of the CMT, and is then sent to areceiver 120, which is configured to demodulate the ASK modulatedsignal, i.e., amplitude modulation OUT, obtaining a received bitstreamRBT. The received bitstream RBT is then demultiplexed by a demultiplexer121, so that at its outputs are present a power control channel on whicha stream of power control value P is transmitted and the n-data channelsD1 . . . Dn.

In one or more embodiments, as shown in FIG. 6 which provides details,the CMT rejection circuit 119 corresponds to the CMT circuit shown indocuments [14], [15], [16]. In particular, the CMT rejection circuit 119is configured to implement CMT filtering by a pass-band amplifier stage24 including a differential amplifier stage—e.g. transistors 24 a, 24 bsuch as FETs—with an (optionally symmetrical) LC resonant load 26 a, 26b.

In one or more embodiments, the LC filter in the resonant load 26 a, 26b may be tuned at a data carrier frequency as used for the (e.g. RFamplitude modulation—ASK) transmission DT, thus rejecting common-modenoise while allowing data transmission.

In one or more embodiments, the LC filter in the stage 24 may provide ahigh Q-factor for common-mode signals to better reject common-modenoise, while resistors 28 a, 28 b may be provided in order to reduce theQ-factor for differential signals to be compliant with data bit rate.

It was noted that the common-mode rejection ratio (CMRR) of a simpledifferential pair (e.g. 24 a, 24 b) without the LC resonant load 26 a,26 b, 28 a, 28 b may be reduced at high frequencies due to the parasiticcapacitance C_(PAR) (e.g. at the FET sources).

Differently from certain conventional solutions, in one or moreembodiments as exemplified herein, the CMTI may be independent of datarate. Moreover, current consumption may be controlled, which may beadvantageous in increasing power efficiency.

Coming back to the general schematics of the converter circuit 110 inFIG. 2, the power control channel, i.e. the channel carrying the powercontrol bits P, is supplied to a digital to analog converter 122 whichconverts the power control P bit stream to an analog control signal. Theanalog control signal is supplied as regulation voltage V_(CTRL) to acorresponding terminal of the power oscillator 112 for power regulation.

Thus, in the implementation just described, the data stream conveyedthrough the amplitude modulation OUT, across the galvanic isolationbarrier represented by transformer 111, includes n-data channel D1 . . .Dn bits and the power control P bits, thus avoiding the use of, atleast, two other isolated links, i.e., one for data transmission and theother for power control feedback, respectively.

In FIG. 3 is shown schematically an embodiment of the converter circuit110, in which the transformer 111 is obtained on a first chip, indicatedwith Chip A (which can be a circuit or an interface, and can be includedin the circuit unit 10 as well), on which the power oscillator 112 isalso incorporated.

As shown, the isolation transformer 111 includes a central tap of thefirst winding 111, splitting the first winding 111 in two half-windings.The first half winding is connected to power supply VDD1 on the firstchip Chip A. The second half winding is connected to ground GND₂ of asecond chip Chip B (which can be a circuit or an interface, and can beincluded in the second circuit unit 12 as well) on which the rectifier113 is present, to help guarantee a low impedance path for the currentinjected by CMT events.

FIG. 3 shows an implementation of the analog to digital converter 116,which is embodied by a simple PWM generator, whose output signal, a PWMsignal representing the power control value P, is then sampled andmultiplexed together with the n channel data D1 . . . Dn. Afterde-multiplexing the received bitstream RBT at demultiplexer 121, adigital to analog conversion is performed on the PWM signal representingthe power control value P bits at the digital to analog converter module122, which is a simple low pass filter, to thereby extract the DCcomponent of the PWM signal, which regulates as per regulation voltageV_(CTRL) at the corresponding regulation terminal of the poweroscillator 12, the transmitted power.

The partition circuit 114 is formed by two equal resistors R, splittingthe value of the output voltage Vo, while the comparator 115 is atrans-conductance amplifier which supplies as error signal ε an errorcurrent I_(ε) driving the PWM generator 116.

To help guarantee the data transmission, the carrier signal, i.e.,amplitude modulation OUT across the galvanic barrier GI, must bepresent. For this reason, a D class power oscillator with on/off controlcannot be used. As shown, there is an oscillator configured as a poweroscillator with a resonant load including two switching MOSFETtransistors M₁ and M₂ connected by a cross-coupled feedback network, andtwo time delay capacitors 2C, i.e., the oscillator is a power oscillatorincluding a cross-coupled pair. The oscillator is operated at acontrolled current. A bias MOSFET M₄ is connected between the source ofthe MOSFETS M₁ and M₂ and the ground GND₁ of the first chip Chip A,providing a minimum bias current for the operation of the oscillator 112under the control of a bias voltage V_(B) applied to its gate electrode.A MOSFET M₃ is then connected between the source of the MOSFETS M₁ andM₂ and the ground GND₁ of the first chip Chip A, and operates as currentgenerator which current is set by the regulation voltage V_(CTRL)received at its gate electrode adjusting the bias current provided byMOSFET M₄. This topology also allows a better CMT rejection compared toa D class oscillator.

Summarizing, such topology includes a power oscillator, i.e., componentsM₁, M₂, 2C, with the cross coupling of MOSFETS, associated with acircuit, i.e., MOSFETs M₄, M₃ for regulating the bias of the poweroscillator M₁, M₂, 2C. The bias MOSFET M₄ is configured to provide aminimum bias current for the operation of the oscillator 112 under thecontrol of a bias voltage V_(B) and a regulation MOSFET M₃ configured toadjust the bias current under the control of the regulation voltageV_(CTRL).

Thus, demultiplexer circuit 121 is used to separate the data streams andextract the signal representing the power control value P bits, which isfiltered to extract the DC component which regulates, as regulationvoltage V_(CTRL), the power of the oscillator 112 by adjusting the biascurrent by means of M₃.

FIG. 4 shows a variant embodiment of the converter 110 in which theisolation transformer 111 is manufactured on a separated chip 31 by adedicated manufacturing process, in particular by post-processing.

To guarantee a correct reconstruction of the transmitted data signals,the implementation here described provides a start-up training phase forthe synchronization between the multiplexer 117 and the demultiplexer121, which is exemplified with reference to FIG. 5, which details theoperation of a converter such as the one of the embodiment shown in FIG.3, i.e. with the transformer 111 on the first chip Chip A.

A respective switch 142 controlled by a switch signal X is placedbetween each input of the multiplexer 117 and the corresponding linecarrying the power control value P or the data channel D1 . . . Dn. Afurther plurality of bit carrying lines 143, on which are interposedrespective switches 144, controlled by the complement of the switchsignal X(bar) feeds to the inputs of the multiplexer 117 logic values,so that the line corresponding to the power control channel, i.e., valueP, is set to logical “1”, while the data channels D1 . . . Dn are set tological “0”.

A timer module 140 is provided on the second chip Chip B, and is drivenby a reference clock signal ck, for instance the main clock of thesecond chip Chip B. The reference clock signal ck is fed to the clockinput of the multiplexer 117. The timer module 140 generates the switchsignal X. During the initial start-up training phase, the switch signalX is set to a logical level, for instance logical “0”, to open theswitches 142 and to close the switches 144, so that bits “1” aretransmitted on the control channel while bits “0” are transmitted on thedata channels. The timer module 141 defines the duration of the start-uptraining phase by controlling the duration at which the signal X is atlevel “0”, and during this time interval the clock reference ck isrecovered from the receiver 120. Specifically, the first pulse ofreference clock ck enables the timer module 140 to set the switch signalX to a low logic level. After a fixed time (for example, after M cyclesof the reference clock signal ck) the switch signal X goes to a highlogic level and the start-up training phase ends. In particular, asshown in FIG. 5, the transmitter 118 includes an encoder 118 a, which isconfigured to perform an encoding, for instance a Manchester encoding toreduce the Bit Error Rate, feeding the encoded signal to a modulator 118b. The modulator 118 b, as mentioned above, applies the correspondingASK modulation by NMOS switches, which shunt to ground two detuningcapacitors, connected to the two ends of the secondary winding 111 s.The receiver 120 includes a corresponding demodulator 120 a demodulatingthe amplitude modulation OUT and supplying a demodulated signal to adecoder 120 b, performing the decoding, to supply the decoded signal,i.e., the received bitstream RBT, to the demultiplexer 121. As shown,the decoder 120 b is also configured to recover the reference clock ckfrom the demodulated signal. The demultiplexer 121 is driven by theselection inputs S_(i) (the number of the enable inputs depends on thenumber of the demultiplexer outputs, in the example of FIG. 5 fouroutputs have been assumed that involve two enable inputs S₁ and S₂)generated by a digital counter 146. The digital counter 146 is driven bythe reference clock ck, as sampling clock, recovered from the decoder120 b. In this way, the selection inputs S₁ and S₂ change at each clockpulse to switch the bits RBT on the different output channels of thedemultiplexer 121. The recovered reference clock ck drives the timermodule 141, that is similar to the timer 140. Specifically, the firstpulse of recovered reference clock ck enables the timer module 141 toclose the switch 147. After a fixed time (for example, after M cycles ofthe recovered reference clock signal ck) the switch 147 is opened andthe start-up training phase ends. The switch 147 is opened and closed,connecting the bitstream RBT to a rising edge detection circuit 145. Acounter 146 is clocked by the reference clock ck and controls theselection input S₁ and S₂ of the outputs of the demultiplexer 121,making it cycle through its outputs, P, D1 . . . Dn, in sequence. Thedetection of a rising edge means that the actual bit in the bitstreamRBT is the control bit and the counter 146 is immediately resetswitching the demultiplexer 121 into the control channel. This happens,during the training phase, where the 10 . . . 0 signal of lines 143 isbeing transmitted as the transmitted bitstream RBT, thus the counter 146switches the demultiplexer on the power control channel P every n+1cycles of the reference clock ck.

When the switch signal X switches, the switches 142 are closed and theswitches 144 open, thus conveying the regular bitstream in which aremultiplexed the control value P and the data channels D1 . . . Dn, whilethe switch 147 is open, cutting off the edge detector 145 so that thecounter 146 cannot be longer reset.

Summarizing in FIG. 5, a switch arrangement 142, 144 is used to feed agiven digital value, i.e., 10 . . . 0, to the multiplexer 117 under thecontrol of a timing signal, i.e., switch signal X, based on a referenceclock signal ck and corresponding switch arrangement, i.e., switch 147.Switch 147 feeds such given digital value to a circuit arrangement,represented by the edge detection circuit 145 and counter 146 performinga reset of the demultiplexer on the basis of the occurrence of the givendigital value in the received bitstream, such occurrence being clockedby the reference clock ck, thus synchronizing the multiplexer 117 anddemultiplexer 121. The timing signal (X) thus identifies a clocktraining phase to synchronize the multiplexer 117 and demultiplexer 121.

Note that in FIG. 5, for simplicity a block 114′ is shown connected withits input to the output Vo and the output to the switching arrangement142, such block including blocks 114, 115 and 116 of FIG. 4.

Without prejudice to the underlying principles, the details and theembodiments may vary, even significantly, with respect to what has beendisclosed by way of example only in the foregoing, without departingfrom the extent of protection.

The extent of protection is defined by the annexed claims.

LIST OF REFERENCES CITED IN THE DESCRIPTION

All of the following references are incorporated herein by reference:

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1. A galvanically isolated DC-DC converter circuit, comprising: a poweroscillator connected to a first winding of an isolation transformerforming a galvanic isolation barrier across which a power signal istransmitted, said galvanic isolation barrier further supporting a datacommunication channel on which a stream of data is conveyed bymodulation of the power signal; a first transmitter configured toamplitude modulate the power signal at a second winding of the isolationtransformer in response to a multiplexed bitstream; a rectifierconnected to the second winding of the isolation transformer andconfigured to obtain an output DC voltage by rectification of the powersignal at the second winding; a comparator configured to compare theoutput DC voltage to a reference voltage value and produce a voltageerror signal; an analog to digital converter configured to convert thevoltage error signal to a digital power control value; a multiplexerconfigured to multiplex the digital power control value with the streamof data to generate the multiplexed bitstream which is applied to thefirst transmitter; a receiver connected to the first winding andconfigured to demodulate the amplitude modulated power signal at thefirst winding; a demultiplexer configured to demultiplex the stream ofdata and the digital power control value; and a digital to analogconverter configured to convert the digital power control value to ananalog control signal to be supplied as a control voltage of the poweroscillator for power regulation.
 2. The galvanically isolated DC-DCconverter circuit according to claim 1, wherein the isolationtransformer is integrated within a dedicated stand-alone chip.
 3. Thegalvanically isolated DC-DC converter circuit according to claim 1,wherein the isolation transformer is within a same chip as the poweroscillator.
 4. The galvanically isolated DC-DC converter circuitaccording claim 1, further comprising a common mode transient (CMT)rejection circuit connected between the first winding and the receiverand configured to reduce effects of common mode transients in theamplitude modulated power signal.
 5. The galvanically isolated DC-DCconverter circuit according to claim 4, wherein the first winding of theisolation transformer has a first central tap connected to a powersupply on a chip containing the power oscillator and the second windingof the isolation transformer has a second central tap connected to aground on a chip containing the rectifier, the first and second centraltaps providing a low impedance path for current injected by common modetransient (CMT) events.
 6. The galvanically isolated DC-DC convertercircuit according to claim 1, wherein the analog to digital convertercomprises a pulse width modulation (PWM) generator generating a PWMoutput signal that is sampled and multiplexed with the stream of data.7. The galvanically isolated DC-DC converter circuit according to claim6, wherein the digital to analog converter comprises a filter configuredto extract a DC component from the PWM output signal, the DC componentserving to regulate power transmitted by the power oscillator.
 8. Thegalvanically isolated DC-DC converter circuit according to claim 1,wherein the power oscillator comprises a cross-coupled pair oftransistors.
 9. The galvanically isolated DC-DC converter circuitaccording to claim 8, wherein the cross-coupled pair of transistors isconnected to a bias regulating circuit for regulating biasing of thecross-coupled pair of transistors, the bias regulating circuit includinga bias MOSFET configured to provide a bias current for operation of thepower oscillator under control of a bias voltage and a regulation MOSFETconfigured to adjust the bias current.
 10. The galvanically isolatedDC-DC converter circuit according to claim 1, further comprising: aswitch arrangement to feed a given digital value to the multiplexerunder control of a timing signal based on a reference clock signal; anda corresponding switch arrangement to feed the given digital value to acircuit arrangement performing a reset of the demultiplexer based uponoccurrence of the given digital value in the stream of data, the timingsignal identifying a clock training phase to synchronize the multiplexerand demultiplexer.
 11. The galvanically isolated DC-DC converter circuitaccording to claim 1, further comprising: a transmitting circuitconfigured to generate the stream of data; and a receiving circuitconfigured to receive the demultiplexed stream of data.
 12. A method forperforming an isolated DC-DC conversion, the method comprising:transmitting on a galvanic isolation barrier a power signal from a DC-DCconverter comprising a power oscillator connected to a first winding ofan isolation transformer, and implementing at least one datacommunication channel by conveying a stream of data through the galvanicisolation barrier by modulating the power signal, the modulatingcomprising performing an amplitude modulation of the power signal at asecondary winding of the isolation transformer; obtaining an output DCvoltage by rectifying the power signal as received at a second windingof the isolation transformer; comparing the output DC voltage with areference voltage value to produce an error signal; converting the errorsignal to a digital power control value; multiplexing the digital powercontrol value with the stream of data to obtain a multiplexed bitstream;driving a transmitter with the multiplexed bitstream, the transmitterperforming the amplitude modulation of the power signal; demodulatingthe amplitude modulated power signal received at the first winding;demultiplexing the stream of data and the digital power control value;converting the digital power control value to an analog control signalto serve as a control voltage of the power oscillator for powerregulation.
 13. The method according to claim 12 further comprisingperforming a synchronization of the multiplexing and demultiplexing byfeeding a given digital value to the multiplexing under control of atiming signal identifying a clock training phase based on a referenceclock signal, and correspondingly feeding the given digital value toperform a reset of the demultiplexer based upon occurrence of the givendigital value in the stream of data.
 14. A DC-DC converter circuit,comprising: an isolation transformer forming a galvanic isolationbarrier across which a power signal is transmitted and across which astream of data is conveyed by modulation of the power signal; a poweroscillator connected to apply an oscillating signal to a first windingof the isolation transformer; a rectifier connected to the secondwinding of the isolation transformer and configured to obtain an outputDC voltage by rectification of the power signal at the second winding;comparison circuitry configured to generate an error signal representinga difference between the output DC voltage and a reference voltagevalue; a transmitter performing an amplitude modulation of the powersignal at a second winding of the isolation transformer in response tothe voltage error signal and the stream of data; and a receiverconfigured to demodulate the amplitude modulated power signal to recoverthe voltage error signal and the stream of data; wherein an amplitude ofthe oscillating signal is controlled as a function of the voltage errorsignal.
 15. The DC-DC converter circuit according claim 14, furthercomprising a common mode transient (CMT) rejection block, connectedbetween the first winding and the receiver, and configured to reduceeffects of common mode transients in the amplitude modulated powersignal.
 16. The DC-DC converter circuit according to claim 15, whereinthe first winding of the isolation transformer has a first central tapconnected to a power supply node and the second winding of the isolationtransformer has a second central tap connected to a ground node.
 17. TheDC-DC converter circuit according to claim 14, wherein the poweroscillator comprises a cross-coupled pair of transistors.
 18. The DC-DCconverter circuit according to claim 17, wherein the cross-coupled pairof transistors is connected to a bias regulating circuit for regulatingbiasing of the cross-coupled pair of transistors, the bias regulatingcircuit including a bias MOSFET configured to provide a bias current foroperation of the power oscillator under control of a bias voltage and aregulation MOSFET configured to adjust the bias current.
 19. The DC-DCconverter circuit according to claim 14, further comprising: amultiplexing circuit configured to time multiplex the voltage errorsignal and the stream of data to generate a signal which controlsamplitude modulation of the power signal by the transmitter.